(a) Technical Field
The present invention relates to a semiconductor device with a metal line and a method of forming the same. More particularly, the present invention relates to a method of forming a metal line in a semiconductor device having the advantages of preventing the penetration of fluorine (F) in an FSG (fluorine-doped silicate glass) layer into a metal line.
(b) Description of the Related Art
As semiconductor devices have become more highly integrated, both a cell size and a pitch of a metal line have been reduced. Such a reduction of a pitch of a metal line may increase the wire resistance and capacitance created between adjacent metal lines. This may result in a lowering of the operation speed of a semiconductor device. Since metal lines having a multi-layer structure are required for solving the above-mentioned problems, a planarization process for an interlayer insulation layer insulating between a lower metal line pattern and an upper metal line pattern is necessarily performed in a multi-layer wiring process.
In addition, as semiconductor devices have become more highly integrated, a space between metal lines has become more narrow. Such a reduction of space between metal lines may induce a parasitic capacitance between adjacent metal lines, and such a parasitic capacitance causes a delay in a time constant (RC) and an increase of power consumption. Therefore, an interlayer insulation layer material having a low-k (low dielectric constant) is required for solving such problems caused by parasitic capacitance. Accordingly, an interlayer insulation layer material may be composed of FSG (fluorine-doped silicate glass) having a dielectric constant of 3 to 3.5 rather than BPSG (boro-phospho-silicate glass), PSG (Phospho silicate glass), and BSG (borosilicate glass), which have a dielectric constant of 4 or more. Generally, an FSG layer is deposited by a HDP CVD (High Density Plasma Chemical Vapor Deposition) method which demonstrates an excellent ability for a gap-fill process, because both deposit and etching are simultaneously performed.
FIG. 1A to FIG. 1D are cross-sectional views showing sequential stages of a conventional method of forming a metal line in a semiconductor device.
As shown in FIG. 1A, a first metal line 120 is formed on a semiconductor substrate 110, and then a protection oxide layer 130 is thinly deposited on the first metal line 120.
In addition, an FSG layer 140 is deposited on the protection oxide layer 130 by using a HDP CVD method.
Subsequently, an upper insulation layer 150 is formed on the FSG layer 140, and a surface of the upper insulation layer 150 is planarized by a CMP (Chemical Mechanical Polishing) process.
In addition, as shown in FIG. 1B, photolithography and etching processes are performed by using a contact mask 160.
Thereafter, as shown in FIG. 1C, a contact hole 151 is formed by etching the upper insulation layer 150 and the FSG layer 140.
As shown in FIG. 1D, a second metal line 170 is formed by depositing a metal material in the contact hole 151.
However, as shown in FIG. 1D, a lateral side of the contact hole 151 contacts the FSG layer 140 in region A. Therefore, fluorine (F) in the FSG layer 140 penetrates into the metal line 170. Consequently, since the metal within the metal line 170 may be contaminated by fluorine (F), the contact resistance may be increased, resulting in a deterioration of the an operation speed of a semiconductor device.
The above information disclosed in this Background section is only for illustrative purposes only, and does not constitute prior art.